1. Field of the Invention
This invention relates to a semiconductor integrated circuit of the insulated gate type and, more particularly, to an output circuit in a semiconductor integrated circuit.
An example of the output circuit in a semiconductor integrated circuit of prior art is shown in FIG. 1. The output circuit is formed of P-channel output transistor Q1, N-channel output transistor Q2, and inverters IN1 and IN2. Inverter IN1 controls the gate voltage PDRl of P-channel transistor Q1, and comprises P-channel transistor Q3 and N-channel transistor Q4. Inverter IN2 controls the gate voltage NDRl of N-channel transistor Q2, and comprises P-channel transistor Q5 and N-channel transistor Q6.
When the above output circuit produces an output voltage OUT of high level "H", both the input signals PDR and NDR input to the inverters IN1 and IN2, which are supplied from a prestige output control circuit (not shown), change from low level "L" to high level "H". When input signals PDR and NDR change from low level "L" to high level "H", the gate voltages PDR1 and NDR1 both change their levels from "H" to "L". In turn, the output transistors Q1 and Q2 become in ON-and OFF-state, respectively. As a result, the output voltage OUT of "H" level is output from the output circuit. Under this condition, no rush-current flows through the path between a VDD power source terminal and a ground power source terminal.
To the contrary, when the output circuit produces an output voltage OUT of low level "L", both the input signals PDR and NDR change their levels from "H" to "L", and the gate voltages PDR1 and NDR1 both change their levels from "L" to "H". In turn, the output transistors Q1 and Q2 become in OFF- and ON-state, respectively. As a result, the output voltage OUT of "L" level is output from the output circuit. Also under this condition, no rush-current flows through the path between a VDD power source terminal and a Vss power source terminal.
Variations of the gate voltage NDR1 and the output voltage OUT of the output circuit with respect to time are illustrated in FIG. 2, when VDD=4.5V and VDD=5.5V. As seen from the figure, the gate voltage NDR1 represented when VDD=5.5V steeply rises more than that represented when VDD=4.5V. This is due to the fact that the drive power of the P-channel transistor Q5 in the inverter IN2, which is represented when VDD=5.5V, is larger than that represented when VDD=4.5V. With the steep rise of the gate voltage, the output voltage OUT falls steeply. An excessively rapid fall of the output voltage, however, causes a variation of the output voltage. This arises from the inductance of the power source line connecting the VDD terminal with the output transistors Q1, and from the inductance of the power source line connecting the ground terminal with output transistor Q2. The voltage output variation may cause noise in the power source line and the ground line in the IC (integrated circuit) chip. The noise may bring about an erroneous operation of the circuit.
A simple measure for the above steep increase problem is to design the transistor Q5 so that the output voltage OUT gently rises for the high power source voltage, e.g., 5.5V. This is attained by determining the size of transistor Q5. However, this measure gives rise to another problem. When the power source voltage is low, e.g., 4.5V, the rise of the output voltage is too gentle. This results in a large delay of the output voltage OUT. The difference between the delay of the output voltage for the low power source voltage (VDD=4.5V) and the delay of the output voltage for the high power source voltage (VDD=5.5V) may be seen in FIG. 2. As seen in the figure, the output delay for the low power voltage (VDD=4.5V) ranges from time point t0 to t1. At time point t0, the output voltage OUT is 4.5V, and steady. At time point t1, the output voltage falls to reach a given voltage 0.8V. For the high power source voltage VDD=5.5V, the output delay ranges from time point t0 to t2. The time delay (t0 to t1) for the low power source voltage is approximately 1.3 times that (t0 to t2) for the high power voltage. Note here that in the semiconductor ICs, the operating speed has been set at the speed determined by the low power voltage. Therefore, when attempt is made to develop high speed semiconductor ICs, the output delay (t0 to t2) for the low power source voltage is the key to the success in the circuit development.
The prior art output circuit has similar problems when it is subjected to a temperature variation. When the output voltage OUT is changed from "H" to "L" level, variations of the gate voltage NDR 1 and the output voltage OUT under operating temperatures Ta=0.degree. C. and Ta=85.degree. C. may be plotted as shown in FIG. 3. When temperature Ta is low, i.e., Ta=0.degree. C., the drive power of the transistor Q5 is high and hence the output voltage steeply falls. When temperature is high, Ta=85.degree. C., the drive power of the transistor is small, and the output voltage OUT gently falls. Therefore, the output delay (t0 to t3) represented when Ta=85.degree. C. is approximately 1.5 times that (t0 to t4) represented when Ta=0.degree. C. Attempt to make the slope of the output voltage waveform more gentle at the low operating temperature Ta, for removing the erroneous operation of the circuit due to the noise in the IC chip, is led to a large output delay at the high temperature. This is a problem when the high speed ICs are handled.